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LH521028
FEATURES * Fast Access Times: 17/20/25/35 ns * Wide Word (18-Bits) for: - Improved Performance - Reduced Component Count - Nine-bit Byte for Parity * Transparent Address Latch * Reduced Loading on Address Bus * Low-Power Stand-by Mode when Deselected * TTL Compatible I/O * 5 V 10% Supply * 2 V Data Retention * JEDEC Standard Pinout * Package: 52-Pin PLCC
52-PIN PLCC
CMOS 64K x 18 Static RAM
operations on the high and the low bytes. The Address Latches are transparent when ALE is HIGH (for applications not requiring a latch), and are latched when ALE is LOW. The Address Latches and the wide word help to eliminate the need for external Address busbuffers and/or latches. Write cycles occur when Chip Enable (E), SH and/or SL, and Write Enable (W) are LOW. The Byte-select signals can be used for Byte-write operations by disabling the other byte during the Write operation. Data is transferred from the DQ pins to the memory location specified by the 16 address lines. The proper use of the Output Enable control (G) can prevent bus contention. When E and either SH or SL are LOW and W is HIGH, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs. Since the device is fully static in operation, new Read cycles can be performed by simply changing the address with ALE HIGH.
PIN CONNECTIONS
TOP VIEW
ALE VCC VSS A15 A14 A0 SL A13
46 45 44 43 42 41 40 39 38 37 36 35 34 DQ8 DQ7 DQ6 VCC VSS DQ5 DQ4 DQ3 DQ2 VSS VCC DQ1 DQ0
SH
A1
W
The LH521028 is a high-speed 1,179,648-bit CMOS SRAM organized as 64K x 18. A fast, efficient design is obtained with a CMOS periphery and a matrix constructed with polysilicon load memory cells. The LH521028 is available in a compact 52-Pin PLCC, which along with the six pairs of supply terminals, provide for reliable operation. The control signals include Write Enable (W), Chip Enable (E), High and Low Byte Select (SL and SH), Output Enable (G) and Address Latch Enable (ALE). The wide word provides for reduced component count, improved density, reduced Address bus loading and improved performance. The wide word also allows for byte-parity with no additional RAM required. This RAM is fully static in operation. The Chip Enable (E) control permits Read and Write operations when active (LOW) or places the RAM in a low-power standby mode when inactive (HIGH).The Byte-select controls, S H and SL, are also used to enable or disable Read and Write
DQ9 DQ10 VCC VSS DQ11 DQ12 DQ13 DQ14 VSS VCC DQ15 DQ16 DQ17
7 8 9 10 11 12 13 14 15 16 17 18 19
65
E
4 3 2 1 52 51 50 49 48 47
20 21 22 23 24 25 26 27 28 29 30 31 32 33
G
FUNCTIONAL DESCRIPTION
A11
VSS
VCC
A10
A12
521028-1D
A4
A2
A3
A5
A6
A8
Figure 1. Pin Connections for PLCC Package
A7
A9
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LH521028
CMOS 64K x 18 Static RAM
ALE
A8 A7 A6 A5 A4 A3 A2 A1 A0
...
DQ0
TRANSPARENT LATCH
DQ8
...
I/O CIRCUIT
SL E W SH
TRANSPARENT LATCH
A15 A14 A13 A12
...
ROW DECODE
BLOCK DECODE
A11 A10 A9
COLUMN DECODE
MEMORY ARRAY (65,536 x 18)
G DQ9
...
DQ17
...
I/O CIRCUIT
...
521028-12
Figure 2. LH521028 Block Diagram
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CMOS 64K x 18 Static RAM
LH521028
TRUTH TABLE
ADDRESS E SH SL ALE G W DQ0-DQ8 DQ9-DQ17 MODE ICC
Don't Care Valid Valid Valid Valid Don't Care Valid Valid Valid Valid Don't Care
H L L L L L L L L L L
X L H L L L L H L H L
X H L L L L H L L H L
H H H H H L H H H H L
X L L L H L X X X X X
X H H H H H L L L L L
High-Z Active High-Z Active High-Z Data Out Data In Don't Care Data In Don't Care Data In
High-Z High-Z Active Active High-Z Data Out Don't Care Data In Data In Don't Care Data In
Standby Read Read Read Read Read Write, low byte Write, high byte Write, both bytes Write, inhibited Write, both bytes
ISB ICC1 ICC1 ICC1 ICC1 ICC1 ICC1 ICC1 ICC1 ICC1 ICC1
NOTE: X = Don't Care, L = LOW, H = HIGH
PIN DESCRIPTIONS
PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN SIGNAL
1 2 3 4 5 6 7 8 9 10 11 12 13
V SS VCC SL SH E A0 A1 DQ9 DQ10 V CC V SS DQ11 DQ12
14 15 16 17 18 19 20 21 22 23 24 25 26
DQ13 DQ14 VSS VCC DQ15 DQ16 DQ17 A2 A3 A4 A5 A6 A7
27 28 29 30 31 32 33 34 35 36 37 38 39
VSS VCC A8 A9 A10 A11 A12 DQ0 DQ1 VCC VSS DQ2 DQ3
40 41 42 43 44 45 46 47 48 49 50 51 52
DQ4 DQ5 VSS VCC DQ6 DQ7 DQ8 A13 A14 A15 G ALE W
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LH521028
CMOS 64K x 18 Static RAM byte and prevent Read or Write operations. When the Select signal is LOW and Chip Enable is LOW, a Read or Write operation is performed at the location determined by the contents of the Address bus. When Chip Enable is HIGH, the Select signals are Don't Care. Select Low (S L) is assigned to DQ0 - DQ8 and Select High (SH) is assigned to DQ9 - DQ17. ALE Address Latch Enable Active High Input
PIN DEFINITIONS
V CC V SS Positive Supply Voltage Terminals Reference Terminals Input
A0 - A15 Address Bus
The Address bus is decoded to select one 18-bit word out of the total 64K words for Read and Write operations. E Chip Enable Active LOW Input
Chip Enable is used to enable the device for Read and Write operations. When HIGH, both Read and Write operations are disabled and the device is in a reduced power state. When LOW, a Read or Write operation is enabled. W Write Enable Active LOW Input
The Address Latch Enable signal is used to control the Transparent latches on the Address bus. The Latches are transparent when HIGH and are latched when LOW. If not required, Address Latch Enable may be tied HIGH, leaving the Address bus in a transparent condition. DQ0 - DQ17 Data Bus Input/Output
Write Enable is used to select either Read or Write operations when the device is enabled. When Write Enable is HIGH and the device is Enabled, a Read operation is selected. When Write Enable is LOW and the device is enabled, a Write operation is selected. A Bytewrite operation is available by using the Byte-select controls. S H, S L Select High Select Low Active LOW Inputs
DQ0 - DQ8 comprise the Low byte, selected by SL, and DQ9 - DQ17 comprise the High Data byte, selected by SH. The Data Bus is in a high impedance input mode during Write operations and standby. The Data bus is in a low-impedance output mode during Read operations. G Output Enable Active LOW Input
The Select High and Select Low signals, in conjunction with the Chip Enable and Write Enable signals, allow the selection of the individual bytes for Read and Write operations. When High, the Select signal will deselect its
The Output Enable signal is used to control the output buffers on the Data Input/Output bus. When G is HIGH, all output buffers are forced to a high impedance condition. When G is LOW, the output buffers will become active only during a Read operation (E and SH / S L are LOW, W is HIGH).
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CMOS 64K x 18 Static RAM
LH521028
ABSOLUTE MAXIMUM RATINGS 1
PARAMETER RATING
VCC to VSS Potential Input Voltage Range DC Output Current
2
-0.5 V to 7 V -0.5 V to VCC + 0.5 V 40 mA -65oC to 150oC 2W
Storage Temperature Range Power Dissipation (Package Limit)
NOTES: 1. Stresses greater than those listed under `Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress rating for transient conditions only. Functional operation of the device at these or any other conditions above those indicated in the `Operating Range' of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time.
OPERATING RANGES
SYMBOL PARAMETER MIN TYP MAX UNIT oC
TA VCC VSS VIL VIH
Temperature, Ambient Supply Voltage Supply Voltage Logic `0' Input Voltage 1 Logic `1' Input Voltage
0 4.5 0 -0.5 2.2 5.0 0
70 5.5 0 0.8 VCC + 0.5
V V V V
NOTE: 1. Negative undershoot of up to 3.0 V is permitted once per cycle.
DC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC1 ISB1
Operating Current 1 Standby Current
tCYCLE = minimum E VCC - 0.2 V VIN VCC - 0.2 V or VIN 0.2 V f=0 E VIH VIN = V IH or VIL VIN = 0 V to VCC VIN = 0 V to VCC IOH = -4.0 mA IOL = 8.0 mA -2 -2 2.4
300 4
mA mA
ISB2 ILI ILO VOH VOL
Standby Current Input Leakage Current I/O Leakage Current Output High Voltage Output Low Voltage
50 2 2
mA A A V
0.4
V
NOTE: 1. ICC is dependent upon output loading and cycle rates. Specified values are with outputs open.
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LH521028
CMOS 64K x 18 Static RAM
AC TEST CONDITIONS
PARAMETER RATING
+5 V
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Ref. Levels Output Load, Timing Tests
VSS to 3 V 5 ns 1.5 V Figure 3
DQ PINS 255 CLOAD=30 pF * 480
CAPACITANCE 1,2
PARAMETER RATING
CIN (Input Capacitance) CDQ (I/O Capacitance)
5 pF
* INCLUDES JIG AND SCOPE CAPACITANCES
7 pF Figure 3. Output Load Circuit
521028-13
NOTES: 1. Capacitances are maximum values at 25oC measured at 1.0 MHz with VBias = 0 V and VCC = 5.0 V. 2. Guaranteed but not tested.
4-216
CMOS 64K x 18 Static RAM
LH521028
AC ELECTRICAL CHARACTERISTICS 1 (Over Operating Range)
SYMBOL DESCRIPTION MIN -17 MAX MIN -20 MAX MIN -25 MAX MIN -35 MAX UNITS
tRC tAA tASL tAHL tLEA tLHM tOH tLH tEA tELZ tEHZ tSA tSLZ tSHZ tGA tGLZ tGHZ tRCS tRCH tPU tPD tWA tWC tEW tSW tAW tAS tAH tASL tAHL tLHW tLHM tWP tDW tDH tWHZ tWLZ
Read Cycle Timing Address Access Time Address Setup to Latch Enable Address Hold from Latch Enable Latch Enable to Data Valid Latch Enable High Pulse Width Output Hold from Address Change Output Hold from Latch High E Low to Valid Data E Low to Output Active S Low to Valid Data S Low to Output Active G Low to Valid Data G Low to Output Active
2,3 2,3 2,3 2,3 2,3
READ CYCLE 17 20 17 3 4 19 5 3 4 17 3 10 9 2 10 8 0 8 0 0
3 3
25 20 25 3 6 22 27 6 5 7 20 25 3 10 10 12 12 3 10 9 12 12 0 8 10 0 0 0 20 25 25 28 25 20 20 20 0 0 3 6 0 6 20 13 0 8 10 3
35 35 3 6 37 6 5 7 35 3 20 20 3 20 20 0 20 0 0 0 35 35 35 30 30 30 0 0 3 6 0 6 30 15 0 14 3
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3 5 5 5 7 3
E High to Output High-Z
2
S High to Output High-Z 2,3
0 0 0 0 17
G High to Output High-Z Read Hold from W Low
Read Setup from W High E LOW to Power Up Time
0 20 WRITE CYCLE 17 13 13 13 0 0 3 4 0 5 13 9 0
E HIGH to Power Down Time
Access Time From Write Enable HIGH Write Cycle Time E Low to End of Write S LOW to End of Write Address Valid to End of Write Address Setup to Start of Write Address Hold from End of Write Address Setup to Latch Enable Address Hold from Latch Enable Latch Hold from W High Latch Enable HIGH Pulse Width W Pulse Width Input Data Setup Time Input Data Hold Time W Low to Output High-Z
2,3
20 15 15 15 0 0 3 5 0 5 15 12 0 8 3
W High to Output Active 2,3
3
NOTES: 1. AC Electrical Characteristics specified at `AC Test Conditions' levels. 2. Active output to High-Z and High-Z to output active tests specified for a 500 mV transition from steady state levels into the test load. CLoad = 5 pF. 3. Guaranteed but not tested.
4-217
LH521028
CMOS 64K x 18 Static RAM Read Cycle No. 2 (Unlatched Chip Enable Controlled Read) Chip is in Read Mode: ALE is HIGH (transparent mode). Read cycle timing is referenced from when E, S, and G are stable until the first address transition. Crosshatched portion of Data Out implies that data lines are in the Low-Z state but the data is not guaranteed to be valid.
TIMING DIAGRAMS - READ CYCLE
Read Cycle No. 1 (Unlatched Address Controlled Read) Chip is in Read Mode: ALE is HIGH (transparent mode), E and G are LOW. Read cycle timing is referenced from when all addresses are stable until the first address transition. Following a W-controlled Write cycle, tWA and tAA must both be satisfied to ensure valid data. Crosshatched portion of Data Out implies that data lines are in the Low-Z state but the data is not guaranteed to be valid until tAA.
tRC
ADDRESS
VALID ADDRESS
tWA
W tAA tOH
DQ
PREVIOUS DATA
VALID DATA
521028-2
Figure 4. Read Cycle No. 1
ADDRESS tRCS
VALID ADDRESS
tRCH
W tEA E tSA SL, SH tGA G tGLZ tSLZ tELZ DQ
VALID DATA
521028-3
tEHZ
tSHZ
tGHZ
Figure 5. Read Cycle No. 2
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CMOS 64K x 18 Static RAM
LH521028
TIMING DIAGRAMS - READ CYCLE (cont'd)
Read Cycle No. 3 (Latched Address Controlled Read) Chip is in Read Mode: W is HIGH, E, SH, SL and G are LOW. Both tAA and tLEA must be met before valid data is available. If the address is valid prior to the rising edge of ALE, then the access time is tLEA. If the address is valid after ALE is HIGH (or if ALE is tied HIGH) then the access time is tAA. Crosshatched portion of Data Out implies that data lines are in the Low-Z state but the data is not guaranteed to be valid until tAA.
E, SH, SL tLHM ALE tASL tAHL
ADDRESS
VALID ADDRESS
tAA
tLH
DQ
PREVIOUS DATA
VALID DATA
tLEA
521028-4
Figure 6. Read Cycle No. 3
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LH521028
CMOS 64K x 18 Static RAM
TIMING DIAGRAMS - READ CYCLE (cont'd)
Read Cycle No. 4 Chip is in Read Mode: Timing illustrated for the case when addresses are valid before E goes LOW. Data Out is not specified to be valid until tEA, tSA and tGA, but may become active as early as tELZ, tSLZ or tGLZ.
tASL ADDRESS
VALID ADDRESS
tAHL
tLHM
ALE tLEA tEA E tRCS tRCH
W
tSA
SL, SH tRC tGA G tGLZ tSLZ tELZ DQ
VALID DATA
521028-5
tEHZ
tGHZ
Figure 7. Read Cycle No. 4
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CMOS 64K x 18 Static RAM
LH521028 Write Cycle No. 1 (Unlatched W Controlled Write) Chip is selected: E, G, and SH / S L are LOW, ALE is High. Using only W to control Write cycles may not offer the best performance since both tWHZ and tDW timing specifications must be met. Write Cycle No. 2 (E, S L, S H Controlled Write) G is LOW. DQ lines may transition to Low-Z if the falling edge of W occurs after the falling edge of E, SH /SL if G is LOW.
TIMING DIAGRAMS - WRITE CYCLE
Addresses must be stable during unlatched Write cycles. The outputs will remain in the High-Z state if W is LOW when E and SH / SL go LOW. If G is HIGH, the outputs will remain in the High-Z state. Although these examples illustrate timing with G active, it is recommended that G be held HIGH for all Write cycles. This will prevent the LH521028's outputs from becoming active, preventing bus contention, thereby reducing system noise.
tWC
ADDRESS
VALID ADDRESS
tAW tAS W tWHZ tWP
tAH
tWLZ tDW tDH
DQ
PREVIOUS OUTPUT
VALID DATA
521028-6
Figure 8. Write Cycle No. 1
tWC
ADDRESS
VALID ADDRESS
tEW
E, SL, SH tAS tWP tAH
W tELZ tWHZ tDW tDH
DQ
VALID DATA
521028-7
Figure 9. Write Cycle No. 2
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LH521028
CMOS 64K x 18 Static RAM
TIMING DIAGRAMS - WRITE CYCLE (cont'd)
Write Cycle No. 3 (Latched W Controlled Write) Chip is selected: E, G, and S H / SL are LOW. Write Cycle No. 4 (E Controlled) G is LOW. DQ lines may transition to Low-Z if the falling edge of W occurs after the falling edges of E and SH/SL.
tWC tLHM
ALE tASL tAHL
ADDRESS
VALID ADDRESS
tAW tAS W tWP
tLHW
tWLZ tWHZ tDW tDH
DQ
PREVIOUS OUTPUT
VALID DATA
521028-8
Figure 10. Write Cycle No. 3
tWC tLHM
ALE tASL tAHL
ADDRESS
VALID ADDRESS
tEW
E, SH / SL tAS tWP tLHW
W tELZ tSLZ DQ tWHZ tDW tDH
VALID DATA
521028-9
Figure 11. Write Cycle No. 4
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CMOS 64K x 18 Static RAM
LH521028
BYTE OPERATIONS
Byte Read Description (Figure 12) To read individual bytes, the device must be enabled (E is LOW), W must be HIGH, the outputs must be enabled (G is LOW) and the addresses must be either stable or latched with ALE. Figure 12 is one example of the byte read capabilities of this device. The example shows two read operations. The first is a read of the high byte of the current memory location and the second is a read of the low byte of the memory location. (1) At the beginning of the cycle both SL and SH are HIGH. (2) SH goes LOW initiating a Read on the upper byte DQH(9-17). SL remains HIGH keeping the lower byte DQL(0-8) disabled and in a high-impedance mode. (3) SL goes LOW activating DQL(0-8).Valid data is available in tSA following SL going LOW. (4) When SH goes HIGH, DQH(9-17) remains valid for tSHZ before returning to a high-impedance condition. (5) Finally, the Read for the lower byte is terminated by deasserting SL (HIGH). DQL(0-8) remains active for tSHZ following SL going HIGH.
ADDRESS
VALID ADDRESS
ALE
G
SL
SH
DQL (0-8)
VALID DATA
DQH (9-17) (1) (2) (3)
VALID DATA
(4)
(5)
521028-10
Figure 12. Byte Read (E is LOW and W is HIGH)
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LH521028
CMOS 64K x 18 Static RAM
BYTE OPERATIONS (cont'd)
Byte Write Description (Figure 13) To do individual byte-write operations, the device must be enabled (E is LOW, G is don't care) and addresses must be either stable or latched. Figure 13 is one example of the byte-write capabilities of this device. The diagram shows two write operations with unlatched addresses. The first is a write to the low byte of memory location N and the second is a write to the high byte of memory location M. (1) W goes LOW while SL and SH remain HIGH. (2) SL goes LOW initiating a Write into the lower byte DQL(0-8) of memory location N. SH remains HIGH preventing a Write into the upper byte DQL(9-17) of memory location N. (3) SL now goes HIGH terminating the Write operation on the lower byte of memory location N. (4) Address N is changed to M. (5) The Write operation is now initiated on the upper byte DQH(9-17) by bringing SH LOW. SL remains HIGH preventing a Write operation from occurring in the lower byte DQL(0-8) of memory location N+ 1. (6) SH now goes HIGH terminating the Write operation on the upper byte of address M. (7) W goes HIGH, ending the Write operation.
ADDRESS
VALID ADDRESS N
VALID ADDRESS M
ALE
W
SL
SH
DQL (0-8)
DATA IN (N)
DQH (9-17)
DATA IN (M)
(1)
(2)
(3)
(4)(5)
(6)
(7)
521028-11
Figure 13. Byte Write (E is LOW)
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CMOS 64K x 18 Static RAM
LH521028
PACKAGE DIAGRAM
52PLCC (PLCC52-P-750)
19.69 [0.775] 18.67 [0.735]
20.57 [0.810] 19.56 [0.770]
18.8 [0.740] 17.78 [0.700]
19.69 [0.775] 18.67 [0.735] 20.57 [0.810] 19.56 [0.770] 4.06 [0.160] 3.56 [0.140]
0.10 [0.004] 1.27 [0.050] TYP. 0.58 [0.023] 0.33 [0.013] 0.76 [0.030] 1.38 [0.015]
MAXIMUM LIMIT DIMENSIONS IN MM (INCHES) MINIMUM LIMIT
52PLCC
52-pin, 750-mil PLCC
ORDERING INFORMATION
LH521028 Device Type U Package - ## Speed 17 20 Access Time (ns) 25 35 52-pin, Plastic Leaded Chip Carrier (PLCC52-P-750) CMOS 64K x 18 Static RAM Example: LH521028U-25 (CMOS 64K x 18 Static RAM, 25 ns, 52-pin, Plastic Leaded Chip Carrier)
521028MD
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